The present invention relates in general to a micro computer system and pertains more particularly to video controller means which form a part of the micro computer system. The video controller in accordance with the present invention provides for video display and is capable of both character generation control and cell generation control along with many other forms of control to be described hereinafter.
It has been common in the past to provide for CPU communication to the video RAM and this occurs usually during a blanking portion of the cycle. This required a waiting period for access and also by use of the blanking period there was apt to be glitches particularly on the left side of the display. This problem has been eliminated and the operation simplified in accordance with the present invention by providing an interlacing concept on the control of a CRT clock signal.
Accordingly, it is an object of the present invention to provide an improved video controller circuit, preferably for use on the micro computer system, and which provides for enhancement of the screen display.
Another object of the present invention is to provide an improved video controller in accordance with the preceding objects and in which communication between the central processing unit and the video RAM is accomplished on an interleaved basis which permits during one portion of the cycle screen refresh and during a second portion of the cycle permits a read/write sequence between the central processing unit and the video RAM.